[2024 Spring] Digital Logic Design
Course Information
| Course | Digital Logic Design | Department | Computer Science and Engineering |
|---|---|---|---|
| Office Hours | TBD | Course No. | 36500-02 |
| Hours | 3.0 | Academic Credit | 3.0 |
| Professor | Yoon, Myung Kuk | Office | Jinseonmi-Gwan, 213 |
| Telephone | (82)-2-3277-3819 | myungkuk.yoon at ewha.ac.kr | |
| Value of Competence | Pursuit of Knowledge (80), Creative Convergence (20) | Keyword | Logic circuits, Combinational Logic, Sequential Logic |
| Class Time | (Wed) 17:00 ~ 18:15 (Fri) 17:00 ~ 18:15 | Class Room | ENGB161 |
Course Description
Digital (or Boolean) Logic is a system of rules that allow us to make complicated decisions based on simple YES/NO (1/0) questions. Students will learn what digital logic is and how digital logic works in this class.
Prerequisites
NONE
Course Format
| Lecture | Discussion/Presentation | Experiment/Practicum | Field Study | Other |
|---|---|---|---|---|
| 100% | 0% | 0% | 0% | 0% |
Course Objectives
In this class, students will be introduced to:
- An overview of integrated circuit technology
- Logic functions and circuits
- Boolean algebra for dealing with logic functions
- Logic gates
- Analysis of circuits
- How transistors operate
- Graphical representation of logic functions in the form of Karnaugh maps
- Representation of numbers in computers
- Circuits used to perform arithmetic operations
- Commonly used combinational sub-circuits
- Multiplexers, Flip-flops, Registers, Shift registers, and so on
- Sequential behavior of digital circuits
- Hardware description languages: VHDL and Verilog
- More if time permits
Evaluation System
Relative + Absolute Evaluation
| Midterm Exam | Final Exam | Quizzes | Presentations | Projects | Assignment | Participation | Other |
|---|---|---|---|---|---|---|---|
| 35% | 35% | 0% | 0% | 0% | 30% | 0% | 0% |
*Evaluation of group projects may include peer evaluations. Explain of evaluation system
- About 35% of students: A
- About 45% of students: B
- About 20% of students: C and below
- If your total score does not exceed 30%, you will get an "F" regardless of the percentage above.
- If you are absent more than five times, you will get an "F."
- If you are late twice, you are considered absent once.
- The course is specifically designed for sophomore students; hence, absences related to job positions or interviews cannot be accepted as excuses.
- Complete your assignments and exams independently. Any instances of plagiarism, whether from fellow students or online sources, will result in an automatic 'F' in this course, regardless of your current standing.
Required Materials
You do NOT need to buy all the books below. You just need one of the books!
-
Fundamentals of Digital Logic with VHDL Design
Stephen Brown and Zvonko Vranesic Edition: Third (3E) ISBN-13: 978-0073529530 ISBN-10: 0073529532
-
Fundamentals of Digital Logic with VHDL Design
Stephen Brown and Zvonko Vranesic Edition: Third (3E) + International ISBN-13: 978-0071268806
-
Fundamentals of Digital Logic with Verilog Design
Stephen Brown and Zvonko Vranesic Edition: Third (3E) ISBN-13: 978-0073380544 ISBN-10: 0073380547
-
Fundamentals of Digital Logic with Verilog Design
Stephen Brown and Zvonko Vranesic Edition: Third (3E) + International ISBN-13: 978-1259072031
Supplementary Materials
NONE
Optional Additional Readings
NONE
Course Contents
| Week | Date | Topics & Materials | Assignement & Quiz |
|---|---|---|---|
| Week #01 | 2024-03-06 (Wed) | CH #00: Digital Logic Design | |
| 2024-03-08 (Fri) | CH #01: Design Concepts | ||
| Week #02 | 2024-03-13 (Wed) | ||
| 2024-03-15 (Fri) | CH #02: Introduction to Logic Circuits | ||
| Week #03 | 2024-03-20 (Wed) | NO CLASS | |
| 2024-03-22 (Fri) | CH #02: Introduction to Logic Circuits | ||
| Week #04 | 22024-03-27 (Wed) | CH #03: Implementation Technology | |
| 2024-03-29 (Fri) | |||
| Week #05 | 2024-04-03 (Wed) | ||
| 2024-04-05 (Fri) | CH #04: Optimized Implementation of Logic Functions | ||
| 2024-04-05 (Fri) | MAKE UP CLASS [18:30 ~ 19:45] | ||
| Week #06 | 2024-04-10 (Wed) | NO CLASS | National Assembly Election |
| 2024-04-12 (Fri) | CH #04: Optimized Implementation of Logic Functions | ||
| Week #07 | 2024-04-17 (Wed) | ||
| 2024-04-19 (Fri) | |||
| Week #08 | 2024-04-24 (Wed) | ||
| 2024-04-24 (Wed) | MIDTERM EXAM REVIEW | MAKE UP CLASS [Recorded Lecture] | |
| 2024-04-26 (Fri) | CH #04: Optimized Implementation of Logic Functions | ||
| 2024-04-27 (Sat) | MIDTERM EXAM | MAKE UP CLASS [10:30 ~ 11:45] | |
| Week #09 | 2024-05-01 (Wed) | NO CLASS | LABOR DAY |
| 2024-05-03 (Fri) | CH #05:Number Representation and Arithmetic Circuits | ||
| Week #10 | 2024-05-08 (Wed) | ||
| 2024-05-10 (Fri) | |||
| Week #11 | 2024-05-15 (Wed) | NO CLASS | BUDDHA's BIRTHDAY |
| 2024-05-17 (Fri) | CH #06: Combinational-Circuit Building Blocks | ||
| 2024-05-17 (Fri) | MAKE UP CLASS [18:30 ~ 19:45] | ||
| Week #12 | 2024-05-22 (Wed) | ||
| 2024-05-24 (Fri) | CH #07:Flip-Flops, Registers, Counters, and a Simple Processor | ||
| Week #13 | 2024-05-29 (Wed) | ||
| 2024-05-31 (Fri) | NO CLASS | A FOUNDATION DAY | |
| Week #14 | 2024-06-05 (Wed) | CH #07:Flip-Flops, Registers, Counters, and a Simple Processor | |
| 2024-06-07 (Fri) | CH #08:Synchronous Sequential Circuits | ||
| Week #15 | 2024-06-12 (Wed) | ||
| 2024-06-14 (Fri) | Semester Summary | ||
| 2024-06-15 (Sat) | FINAL EXAM | MAKE UP CLASS [10:30 ~ 11:45] | |
| Week #16 | 2024-06-19 (Thu) | NO CLASS | |
| 2024-06-21 (Fri) | Final Exam Review (Nonmandatory) |
Course Policies
*For laboratory courses, all students are required to complete lab safety training.
Special Accommodations
*According to the University regulation #57, students with disabilities can request special accommodation related to attendance, lectures, assignments, and/or tests by contacting the course professor at the beginning of semester. Based on the nature of the students’ requests, students can receive support for such accommodations from the course professor and/or from the Support Center for Students with Disabilities (SCSD).
Extra Information
The contents of this syllabus are not final—they may be updated.