Intelligence System and Parallel Computer Architecture Lab

Intelligence system and Parallel Computer Architecture (IP-CAL) Lab was founded in March 2021. Our lab is located in Ewha Womans University. Our research interests are Graphics Processing Units (GPU), machine learning accelerators, parallel programming, and computer architecture. Detailed research topics are described below. If you are interested in the topics, you are always welcome to visit our lab.

Graphics Processing Unit (GPU) Micro-Architecture

GPUs were first developed to accelerate graphics applications. Games are one major application that relies on the performance of GPUs. When the game application is launched, GPUs start to create 60~120 images every second using a massive number of GPU processors. This massive number of processors recently has begun to be used for general purpose applications such as machine learning algorithms, simulations, and many other applications instead of graphics applications. This paradigm is known as General-Purpose Computing on Graphics Processing Unit (GPGPU).

Our goal is to maximize the performance of GPUs when general-purpose applications such as machine learning algorithms, simulations, and many more are executed on the GPU hardware. We first identify the bottleneck points on the GPU architecture and propose a new modified architecture that can remove the bottleneck points. To verify our ideas, C/C++/Python based cycle-accurate simulations are used.

Machine Learning Accelerator

Machine learning algorithms have been applied in various areas such as image recognition, voice speech recognition, translation, text classification, and more. These algorithms are traditionally operated on Central Processing Units (CPUs) and Graphics Processing Units (GPUs). Especially, GPUs are widely used for the execution of applications. However, CPUs and GPUs are not designed for machine learning algorithms, there have been several issues in terms of performance and power consumption. To resolve the problems, various machine learning accelerator designs have been proposed by researchers. One famous design is using a systolic array that has many small processing units which are only designed to perform Multiply-And-Accumulate (MAC) operations. These small processing units are connected only to their neighbor so that the data can be transferred from one processing unit to the other processing unit.

Our goal is to analyze the newly proposed machine learning accelerators. By doing this, we can find the performance bottleneck points or can detect the unnecessary processing execution cycles. Based on our analysis, we can propose advanced hardware accelerators for machine learning applications.

Parallel Programming

Single Instruction Multiple Data (SIMD) and Single Instruction Multiple Threads (SIMT) are execution models used in parallel computing. In these models, multiple threads (data) are executed in lock-step. These models are widely used for supercomputers because of their efficiency.

Intel and AMD CPUs have vector processors (SIMD) that can be used by Advanced Vector Extension (AVX) instructions. In the case of NVIDIA GPUs, Compute Unified Device Architecture (CUDA) allows software developers to use massively parallel SIMT processors for general purpose applications. The developers must have a decent knowledge of the vector processing units in order to create efficient applications. Our goal is to provide proper knowledge to software developers so that the developers can create efficient programs.

Computer Architecture

Computer Architecture is a set of rules which state how hardware is connected together in order to compute complicated applications. Researchers have proposed many different techniques such as branch predictions, speculative execution, out-of-order execution, memory pre-fetching, and more. We use C/C++/Python based cycle-accurate simulations to study the previously proposed techniques.

IP-CAL News!

  • [2024. 11.] Congratulation

    The paper titled "Warped-Compaction: Maximizing GPU Register File Bandwidth Utilization via Operand Compaction" by Eunbi has been accepted to HPCA 2025 (Top-Tier).

    [2024. 09.] Welcome

    Jane Rhee, Eunbi Jeong, Seonwoo Kim have started their master's degree.

    [2024. 03.] Welcome

    Eun Soo Jung and Jiyeong Yi have started their master's degree.

    [2024. 02.] Congratulation

    "Conflict-Aware Compiler for Hierarchical Register File on GPUs" by Eunbi and Eun Seong has been accepted in the Journal of Systems Architecture (JSA).

    [2024. 01.] Welcome

    Jiyeong Yi has joined our group as undergraduate interns.

    [2023. 08.] Congratulation

    Eunbi's first co-authored paper, "Triple-A," has been accepted in IEEE Embedded System Letters (ESL).

    [2023. 07.] Congratulation

    Eun Seong and Eunbi are honored with the Paper Award (우수논문상) at the 2023 Summer Annual Conference of IEIE.

    [2023. 07.] Welcome

    Ikyoung Choi has joined our group as undergraduate interns.

    [2023. 04.] Welcome

    Seonwoo Kim has joined our group as undergraduate interns.

    [2023. 01.] Welcome

    Jae Eun Hwang and Eunbi Jeong have joined our group as undergraduate interns.

    [2022. 01.] Welcome

    Eun Soo Jung, Yeonhee Jung, and Eun Seong Park have joined our group as undergraduate interns.

    [2021. 07.] Welcome

    Minyoung Lee, Jane Rhee, and Myeong Ji Kim have joined our group as undergraduate interns.