[2025 Spring] Digital Logic Design


Course Information

Course Digital Logic Design Department Computer Science and Engineering
Office Hours TBD Course No. 36500-02
Hours 3.0 Academic Credit 3.0
Professor Yoon, Myung Kuk Office Jinseonmi-Gwan, 213
Telephone (82)-2-3277-3819 E-Mail myungkuk.yoon at ewha.ac.kr
Value of Competence Pursuit of Knowledge (80), Creative Convergence (20) Keyword Logic circuits, Combinational Logic, Sequential Logic
Class Time (Wed) 17:00 ~ 18:15
(Fri) 17:00 ~ 18:15
Class Room ENGB152

Course Description

Digital (or Boolean) Logic is a system of rules that allow us to make complicated decisions based on simple YES/NO (1/0) questions. Students will learn what digital logic is and how digital logic works in this class. * The primary syllabus used for this course is from the website rather than the traditional school system. Consequently, any significant updates or changes will be made exclusively to the web syllabus.


Prerequisites

NONE


Course Format

Lecture Discussion/Presentation Experiment/Practicum Field Study Other
100% 0% 0% 0% 0%

Course Objectives

In this class, students will be introduced to:

  1. An overview of integrated circuit technology
  2. Logic functions and circuits
  3. Boolean algebra for dealing with logic functions
  4. Logic gates
  5. Analysis of circuits
  6. How transistors operate
  7. Graphical representation of logic functions in the form of Karnaugh maps
  8. Representation of numbers in computers
  9. Circuits used to perform arithmetic operations
  10. Commonly used combinational sub-circuits
  11. Multiplexers, Flip-flops, Registers, Shift registers, and so on
  12. Sequential behavior of digital circuits
  13. Hardware description languages: VHDL and Verilog
  14. More if time permits

Evaluation System

Relative + Absolute Evaluation

Midterm Exam Final Exam Quizzes Presentations Projects Assignment Participation Other
35% 35% 0% 0% 0% 30% 0% 0%

*Evaluation of group projects may include peer evaluations.

Explain of evaluation system

  1. About 35% of students: A
  2. About 45% of students: B
  3. About 20% of students: C and below

Further details regarding the letter grade and attendance:
  1. If your total score is above 20% but does not exceed 30%, you will receive a “D” regardless of the percentage above.
  2. If your total score does not exceed 20%, you will receive an “F” regardless of the percentage above.
  3. If you are absent more than five times, you will get an "F."
  4. If you are late twice, you are considered absent once.
  5. The course is specifically designed for sophomore students; hence, absences related to job positions or interviews cannot be accepted as excuses.
  6. Complete your assignments and exams independently. Any instances of plagiarism, whether from fellow students or online sources, will result in an automatic 'F' in this course, regardless of your current standing.


Required Materials

You do NOT need to buy all the books below. You just need one of the books!

  • Fundamentals of Digital Logic with VHDL Design

    Stephen Brown and Zvonko Vranesic
    Edition: Third (3E)
    ISBN-13: 978-0073529530
    ISBN-10: 0073529532

  • Fundamentals of Digital Logic with VHDL Design

    Stephen Brown and Zvonko Vranesic
    Edition: Third (3E) + International
    ISBN-13: 978-0071268806

  • Fundamentals of Digital Logic with Verilog Design

    Stephen Brown and Zvonko Vranesic
    Edition: Third (3E)
    ISBN-13: 978-0073380544
    ISBN-10: 0073380547

  • Fundamentals of Digital Logic with Verilog Design

    Stephen Brown and Zvonko Vranesic
    Edition: Third (3E) + International
    ISBN-13: 978-1259072031


Supplementary Materials

NONE


Optional Additional Readings

NONE


Course Contents

Week Date Topics & Materials Etc.
Week #01 2025-03-05 (Wed) CH #00: Digital Logic Design Recorded Lecture
2025-03-07 (Fri) CH #01: Design Concepts Recorded Lecture
Week #02 2025-03-12 (Wed)
2025-03-14 (Fri) CH #02: Introduction to Logic Circuits
Week #03 2025-03-19 (Wed)
2025-03-21 (Fri)
Week #04 22025-03-26 (Wed)
2025-03-28 (Fri) CH #03: Implementation Technology
Week #05 2025-04-02 (Wed)
2025-04-04 (Fri) CH #04: Optimized Implementation of Logic Functions
Week #06 2025-04-09 (Wed)
2025-04-11 (Fri)
Week #07 2025-04-16 (Wed)
2025-04-18 (Fri)
Week #08 2025-04-23 (Wed)
2025-04-25 (Fri)
Week #09 2025-04-30 (Wed) CH #05:Number Representation and Arithmetic Circuits
2025-05-02 (Fri)
2025-05-03 (Sat) MIDTERM EXAM MAKE UP CLASS [09:00 ~ 10:15]
Week #10 2025-05-07 (Wed) CH #05:Number Representation and Arithmetic Circuits
2025-05-09 (Fri)
Week #11 2025-05-14 (Wed) CH #06: Combinational-Circuit Building Blocks
2025-05-16 (Fri)
Week #12 2025-05-21 (Wed)
2025-05-23 (Fri) CH #07:Flip-Flops, Registers, Counters, and a Simple Processor
Week #13 2025-05-28 (Wed)
2025-05-30 (Fri) NO CLASS EWHA's 139th Anniversary Ceremony
Week #14 2025-06-04 (Wed) CH #08:Synchronous Sequential Circuits
2025-06-06 (Fri) NO CLASS Memorial Day
Week #15 2025-06-11 (Wed) CH #08:Synchronous Sequential Circuits
2025-06-13 (Fri) Semester Summary
2025-06-14 (Sat) FINAL EXAM MAKE UP CLASS [09:00 ~ 10:15]
Week #16 2025-06-18 (Thu) NO CLASS
2025-06-20 (Fri) Final Exam Review (Nonmandatory)


Course Policies

*For laboratory courses, all students are required to complete lab safety training.


Special Accommodations

*According to the University regulation #57, students with disabilities can request special accommodation related to attendance, lectures, assignments, and/or tests by contacting the course professor at the beginning of semester. Based on the nature of the students’ requests, students can receive support for such accommodations from the course professor and/or from the Support Center for Students with Disabilities (SCSD).


Extra Information

The contents of this syllabus are not final—they may be updated.